The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More specifically, the invention relates to an insulated-gate field-effect transistor and a bipolar transistor, both formed on an SOI substrate.
In a high breakdown voltage semiconductor device formed on the SOI (Silicon On Insulator) substrate, the magnitude of the breakdown voltage of the device determines the thickness of a silicon layer and the thickness of a buried insulating film. The silicon layer is the active region where the device is formed, and is formed over a support silicon substrate via the insulating film. The breakdown voltage of an N-channel insulated-gate field-effect transistor is herein defined as a voltage applied to a drain electrode therein when an electric current flowing through the drain electrode has become 10 xcexcA through the application of the voltage to the drain electrode. In this case, the gate width of the field-effect transistor measured with an IWATSU semiconductor curve tracer TT-508 is 50 xcexcm, and source and gate electrodes and the back of the SOI substrate where the device is formed are set at the ground level or 0 V. Alternatively, the breakdown voltage of a P-channel insulated-gate field-effect transistor is herein defined as a voltage applied to a source electrode or a gate electrode therein when a current flowing through the source electrode has become 10 xcexcA through the application of voltages applied to both the source and gate electrodes. In this case, the gate width of the field-effect transistor measured with the above-mentioned curve tracer is 50 xcexcA, and a drain electrode and the back of an SOI substrate is set at the ground level (0 V). Alternatively, the breakdown voltage of an NPN bipolar transistor is herein defined as a voltage applied to a collector electrode therein, or BVceo when a current flowing through the collector electrode has become 10 xcexcA through the application of the voltage to the collector electrode. The emitter length of the bipolar transistor measured with the curve tracer is 50 xcexcm in this case, and the base electrode is set to open, and an emitter electrode and the back of an SOI substrate are set at the ground level. Still alternatively, the breakdown voltage of a PNP bipolar transistor is herein defined as a voltage applied to an emitter electrode therein when a current flowing through the emitter electrode has become 10 xcexcA through the application of the voltage applied to the emitter electrode. In this case, a collector electrode and the back of an SOI substrate is set at the ground level and a base electrode is set to open by the use of the above-mentioned curve tracer.
The thicker the silicon layer and the thicker the buried insulating film, a device with an increased breakdown voltage can be fabricated. However, when the buried insulating film becomes thick, a warp in a wafer increases in the manufacturing process of the device. Consequently, the process at the final stage in completion of the device cannot be performed. Further, the larger a wafer diameter, the more manifest this phenomenon becomes. In general, in the wafer with a diameter of 6, 8, or 12 inches, a silicon oxide film is now commonly employed as the buried insulating film. The maximum thickness of the buried insulating film is regarded as approximately 3 xcexcm. For this reason, when a high breakdown voltage device is fabricated, it is necessary to increase the thickness of the silicon layer, which is the active region. However, if the thickness of the silicon layer is increased, it takes much time to form trenches required for isolation of a device-forming region. For this reason, throughput is reduced, so that a cost problem arises. In addition, it becomes difficult to form a completely vertical deep trench and cover the trench with an insulated film tightly.
FIGS. 2A and 2B show the structure of a high breakdown voltage N-channel MOS field-effect transistor and the structure of a high breakdown voltage NPN bipolar transistor, both using an SOI substrate with an N-type device-forming region and having a breakdown voltage of approximately 200 to 600 V, respectively.
FIG. 2A illustrates the N-channel MOS field-effect transistor formed on an SOI substrate 101 having an N-type region over a buried insulating film 103. The transistor comprises a high concentration N-type layer 402 and a high concentration p-type layer 401 both contacting a source electrode 201, a gate insulating film 301 and a gate electrode 302, a high concentration N-type layer 403, and a p-type semiconductor layer or a p-body layer 404. The gate insulating film 301 and the gate electrode 302 are in contact with the high concentration N-type layer 402. The high concentration N-type layer 403 is in contact with a drain 202 disposed in a lateral direction via a field oxide film 204 contacting the gate electrode. The p-body layer 404 is in contact with the gate oxide film, and the high concentration N-type and P-type layers contacting the source electrode. As a drain region interposed between the p-body layer and the drain electrode, the N-type substrate is usually employed without alteration. Alternatively the concentration of the drain region may be adjusted by ion implantation and diffusion of phosphorus ions, for example. An n-type layer formed by implantation and diffusion of ions of an element such as phosphorus into the substrate is hereinafter referred to as a WELL and the concentration of the resulting layer is referred to as a WELL concentration.
FIG. 2B illustrates the NPN bipolar transistor formed on the SOI substrate 101 having the N-type region over the buried insulating film 103. The transistor comprises a collector electrode 205, an emitter electrode 207 and a base electrode 206 disposed via the field oxide film 204, high-concentration N-type layers 411 and 413, a high concentration P-type layer 412, and a P-type base region 414. The high-concentration N-type layer 411 is in contact with the collector electrode. The high concentration N-type layer 413 is in contact with the emitter electrode 207. The high concentration P-type layer 412 is in contact with the base electrode. The p-type base region 414 is in contact with the high concentration N-type layer contacting the emitter electrode and the high concentration P-type layer contacting the base electrode. As a collector region interposed between the p-type base region and the collector electrode, the n-type substrate is usually employed without alteration, or the WELL is formed for use as the collector region. The NPN bipolar transistor is usually what is called a vertical structure with a high concentration N-type layer brought into contact with the buried insulation film. However, the present invention has been made to reduce the thickness of the silicon layer. Accordingly, if the high concentration N-type layer is present in the silicon layer with its thickness reduced, a high breakdown voltage cannot be obtained. Thus, a lateral structure in which the high concentration N-type layer contacting the buried insulating film has been solely removed from the conventional vertical structure is herein defined as a conventional structure.
Now, a mechanism whereby a breakdown voltage is determined will be described. In the case of the N-channel MOS field-effect transistor illustrated in FIG. 2A, when a voltage is applied to the drain electrode, a depletion layer formed between the p-body layer and the N-type substrate is extending. In addition, a depletion layer is extending from the vicinity of the buried insulating film under the drain electrode as well. If a drain-source distance is short, a rise in the electric field of the depletion layer formed between the p-body layer and the N-type substrate becomes faster than a rise in the electric field of the depletion layer formed in the vicinity of the buried insulating film. If the drain-source distance becomes long, the depletion layer between the p-body layer and the N-type substrate can extend sufficiently large. Accordingly, a rise in the electrical field of the depletion layer formed in the vicinity of the buried insulating film becomes faster than a rise in the electric field of the depletion layer formed between the p-body layer and the N-type substrate. The drain-source distance is affected by the concentration of the substrate as well. When the concentration of the substrate becomes high, even if the drain-source distance is increased, the depletion layer formed between the p-body layer and the N-type substrate cannot extend sufficiently large. Thus, the breakdown voltage is determined from the depletion layer between the p-body layer and the N-type substrate. Suppose selection of the concentration of the substrate is performed so that the breakdown voltage is determined from the extension of the depletion layer formed in the vicinity of the buried insulating film. Then, the maximum breakdown voltage of the device with a given silicon layer thickness and a given buried-insulating-film thickness can be obtained.
In the case of the NPN bipolar transistor illustrated in FIG. 2B as well, the breakdown voltage is determined either from the electric field of the depletion layer formed between the P-type base layer and the N-type substrate or the electric field of the depletion layer that extends from the buried insulating film immediately under the collector electrode, as in the case of the N-channel MOS field-effect transistor. In the case of the NPN bipolar transistor as well, by selecting the concentration of the substrate such that the breakdown voltage is determined from the extension of the depletion layer from the vicinity of the buried insulating film, the breakdown voltage can be maximized.
When an N-channel MOS field-effect transistor having the conventional structure is formed on the SOI substrate including a 1.5-xcexcm thick silicon layer and a 3.0-xcexcm thick silicon oxide film employed as the buried insulating film, the breakdown voltage of the device becomes 275 V according to a computer simulation. Thus, it becomes impossible to achieve the breakdown voltage of 300 V. For this reason, if the N-channel MOS field-effect transistor with the breakdown voltage of 300 V is desired, there is no way other than increasing the thickness of the silicon layer or the thickness of the buried oxide film.
However, in the case of an 8-inch SOI substrate, for example, when the thickness of the buried oxide film exceeds 3.0 xcexcm, a warp in the wafer increases during the manufacturing process of the device, so that manufacture of the device cannot be completed.
Even when the thickness of the buried oxide film is 3.0 xcexcm as well, in order to reduce a warp on the wafer in the initial state, a thick oxide film with a thickness of 2.0 xcexcm or more should be formed over the region of the SOI substrate surface that is not the device-forming region, at the purchase of the wafer. Then, during the device manufacturing process as well, care should be taken so as not to reduce the thickness of the oxide film as much as possible. Accordingly, a reduction in the thickness of the buried oxide film is desired. On the other hand, when the thickness of the silicon layer becomes thick, it takes additional time to form the trenches for device isolation. Thus, throughput is reduced, and it also becomes difficult to form a vertical deep trench and cover the trench with an insulating film tightly. For this reason, a reduction in the thickness of the silicon layer is also desired.
The present invention has been made in view of the problems described above. It is therefore an, object of the present invention to provide an increased breakdown voltage semiconductor device and the method of manufacturing the increased breakdown voltage semiconductor device without increasing the thickness of a silicon layer that is a device active region. The semiconductor device according to the present invention comprises either an insulated-gate field-effect transistor and a bipolar transistor, both having an increased breakdown voltage.
As an attempt to increase the breakdown voltage of a semiconductor device on an SOI substrate, there is provided an invention, as described in JP-A-08-181321, that aims at improvement in the breakdown voltage by forming an N-type high concentration layer near a buried insulating film. However, suppose a semiconductor device on a thin SOI substrate including a silicon layer having a thickness of approximately 2 xcexcm or less, as suggested by the present invention. If the N-channel MOS field-effect transistor illustrated in FIG. 2A is taken as an example, the depletion layer between the p-body layer and the N-type substrate comes in contact with the N-type high concentration layer near the buried oxide film. Thus, the breakdown voltage of the device is not increased. On the contrary, it is reduced. Likewise, even in the NPN bipolar transistor illustrated in FIG. 2B, the depletion layer between the p-base layer and the N-type substrate comes into contact with the N-type high concentration layer near the buried oxide film, the breakdown voltage of the device is not increased. On the contrary, it is reduced.
There is also provided an invention disclosed in FIG. 157 in U.S. Pat. No. 5,640,040 which aims at an improvement in the breakdown voltage by forming an N-type layer under a cathode. However, on the SOI substrate with the 1.5-xcexcm thick silicon layer and the 3.0-xcexcm thick buried oxide film, suggested by the present invention, the structure according to this U.S. patent cannot achieve the breakdown voltage of 300 V.
In order to solve the problems described above, an N-channel MOS field-effect transistor according to a first aspect of the invention comprises an N-type region having a concentration higher than the concentration of a region contacting a p-body layer. The N-type region constitutes a region covering at most 95% of the distance from the end of a source region to the end of a drain region. The N-type region is in contact with a high concentration N-type layer contacting a drain electrode and extends toward a high concentration N-type layer in contact with a source electrode. The end of the source region is herein defined as the end of a gate oxide film contacting the high concentration N-type layer in contact with the source electrode. The end of the drain region is herein defined as the end of a field oxide film contacting the high concentration N-type layer in contact with the drain electrode.
An NPN bipolar transistor according to the first aspect of the present invention also comprises an N-type region having a concentration higher than the concentration of a region contacting a P-type base region. The N-type region constitutes a region covering at most 95% of the distance from the end of a collector region to the end of a base region. The N-type region is in contact with a high concentration N-type layer contacting a collector electrode and extends toward the base region. The end of the collector region is herein defined as the end of a field oxide film in contact with the high concentration N-type layer contacting the collector electrode. The end of the base region is herein defined as the end of the filed oxide film contacting the base region.
There are two types of mechanisms whereby the breakdown voltage of a semiconductor device formed on the SOI substrate having an N-type device-forming region is determined. In the above-mentioned N-channel MOS field-effect transistor, for example, the breakdown voltage is determined from an electric field resulting from extension of a depletion layer formed between the p-body layer and the substrate. Alternatively, the breakdown voltage is determined from an electric field resulting from extension of a depletion layer formed in the vicinity of the buried insulating film. The concentration of the substrate or WELL concentration determines which one of the mechanisms is employed. More specifically, when the concentration of the substrate is low, the depletion layer formed between the-p-body layer and the N-type substrate can extend sufficiently large. For this reason, a rise in the electric field of the depletion layer formed in the vicinity of the buried oxide film becomes faster than a rise in the electric field of this depletion layer. A critical voltage is thus reached faster in the electric field of the depletion layer in the vicinity of the buried oxide film. However, when the concentration of the substrate becomes high, the depletion layer formed between the p-body layer and the N-type substrate cannot extend sufficiently large. Thus, the critical voltage is reached faster in the electric field of the depletion layer between the p-body layer and the N-type substrate than the electric field of the depletion layer formed in the vicinity of the buried insulating film.
However, when a voltage close to the breakdown voltage is applied to the N-type MOS field-effect transistor illustrated in FIG. 2A, the N-type layer excluding the p-body layer becomes fully depleted, so that it can be regarded as a single capacitor. Its capacitance is denoted Csi. The buried insulating film, for which a silicon oxide film is employed in many cases, has also a capacitance as a matter of course. This capacitance is denoted Cox. Then, when the voltage close to the breakdown voltage is applied, the SIO substrate can be modeled as a series connection of the capacitors of Csi and Cox. Usually, a support substrate under the buried oxide film also has a capacitance. However, in a computer simulation employed for the present invention, the support substrate is regarded as a complete conductor, and approximations are made on the basis of this assumption. Further, modeling is performed such that the potential of the interface of the support substrate contacting the buried oxide film is set to the ground potential. Thus, the capacitance of the support substrate is ignored in this modeling process as well. When a voltage V is applied to the drain electrode, the applied voltage V is divided between the silicon substrate and the buried oxide film according to the ratio between the capacitance Csi and the capacitance Cox. The voltage applied to the buried oxide film when the voltage V is applied to the drain electrode can be expressed as (Csixc3x97V)/(Csi+Cox). The larger Csi becomes, the larger the voltage applied to the buried oxide film can be made. Consequently, the voltage applied to the silicon substrate is accordingly reduced. The breakdown voltage of the device is thus improved. Setting the Csi to be large or setting the concentration of the substrate to be high can increase the voltage applied to the buried oxide film. The breakdown voltage of the device is thereby improved.
The excessively high concentration of the substrate, however, does not allow the depletion layer formed between the p-body layer and the N-type substrate to extend sufficiently large. For this reason, the breakdown voltage of the device is determined from the depletion layer formed between the p-body layer and the N-type substrate. Consequently, the breakdown voltage is not improved. On the contrary, it is reduced. Accordingly, provided that the depletion layer formed between the p-body layer and the N-type substrate can be extended sufficiently large, the increased concentration of the substrate can provide a higher breakdown voltage. Hence, if a voltage applied to the buried oxide film can be increased or the concentration of the substrate can be increased while the depletion layer formed between the p-body layer and the N-type substrate is extended sufficiently large, the breakdown voltage of the device can be improved without increasing the thickness of the silicon layer.
The first feature of the present invention is that the substrate concentration of a region between the p-body layer and the N-type substrate, where the depletion layer is formed, is set to be low, and that the concentration of other region is set to be higher than the substrate concentration. The breakdown voltage of the device is not thereby determined from extension of the depletion layer between the p-body layer and the N-type layer, but is determined from extension of the depletion layer formed in the vicinity of the buried oxide layer. With this arrangement, the concentration of the substrate other than a region near the p-body layer can be made higher than that in the conventional structure. Thus, a voltage applied to the buried oxide film is increased, which results in an improvement in the breakdown voltage.
FIG. 3 shows the breakdown voltage obtained when the proportion of the N-type layer formed in the structure of the NPN bipolar transistor according to the present invention is changed relative to a collector-base distance. This structure is formed on the SOI substrate including the 1.5-xcexcm thick silicon layer and a 0.5-xcexcm thick buried oxide film, and the concentration of the substrate is 5xc3x971015/cm3. Formation of the N-type layer having a concentration higher than the concentration of the substrate, which is the feature of the present invention, starts from the end of the collector region. In the conventional NPN transistor structure, when the concentration of the substrate is 5xc3x971015/cm3, the breakdown voltage is 95 V, according to the computer simulation. Suppose that the present invention is applied to the NPN bipolar transistor having the concentration of the substrate of 5xc3x971015/cm3. If the proportion of the formed N-type layer exceeds 0% of the emitter-base distance or if any N-type region with a concentration higher than the concentration of the substrate is present, the effect of the present invention can be obtained. The effect brings about an increase in the breakdown voltage of approximately 30 V at the maximum. The breakdown voltage becomes as large as 125 V at the maximum. The effect can be obtained until the proportion of the N-type layer with the concentration higher than the concentration of the substrate reaches 95% of the collector-base distance.
In an N-channel MOS field-effect transistor according to a second aspect of the present invention, the concentration of an N-type layer in contact with a buried insulating film under a drain electrode is set to be from 3xc3x971016/cm3 to 1xc3x971022/cm3. In an NPN bipolar transistor, the concentration of an N-type layer in contact with a buried insulating film under a collector electrode is set to be from 3xc3x971016/cm3 to 1xc3x971022/cm3.
With this arrangement, in the N-channel MOS field-effect transistor, a depletion layer from the buried insulating film under the drain electrode does not extend, so that a voltage input to the drain electrode is all applied to the buried insulating film. Consequently, the breakdown voltage of the device is more improved than in the conventional structure. Incidentally, phosphorus and arsenic-are suitable for making the concentration of the N-type layer to be from 3xc3x971016/cm3 to 1xc3x971022/cm3. A CAMECA secondary ion mass spectrometer (SIMS) IMS-6F is employed for identification of the concentration, and Cs+ ions are used as primary ions.
There will be many cases where the concentration is used for describing the features of the present invention. The SIMS system described above will be employed for identification of the concentration in a region.
In a P-channel MOS field-effect transistor formed on an SOI substrate having an N-type device-forming region as well, on the other hand, the same effect as that according to the second aspect of the present invention can be obtained. In the P-channel MOS field-effect transistor, a voltage is usually applied to a source electrode. For this reason, a depletion layer extends from the vicinity of a buried insulating film under the source electrode. The breakdown voltage determined from this depletion layer takes on a maximum value. Accordingly, if an N-type layer with a concentration ranging from 3xc3x971016/cm3 to 1xc3x971022/cm3 is formed in the vicinity of the buried insulating film under the source electrode, depletion does not occur from there. Thus, a voltage input to the source electrode is all applied to the buried insulating film, so that the breakdown voltage is improved.
In a PNP bipolar transistor as well, if an N-type layer with a concentration ranging from 3xc3x971016/cm3 to 1xc3x971022/cm3 is formed under a base region, the breakdown voltage is improved.
According to the first aspect of the present invention, a region covering at most 95% of the source-drain distance is set to the N-type layer having a concentration higher than the concentration of the substrate. According to the second aspect of the present invention, the concentration of the N-type layer in contact with the buried insulating film under the drain electrode is set to be from 3xc3x971016/cm3 to 1xc3x971022/cm3. In the N-channel MOS field-effect transistor according to the present invention, combination of the first aspect of the present invention and the second aspect of the present invention is possible as a matter of course. Then, the breakdown voltage of the device is further improved. In the NPN bipolar transistor according to the present invention as well, combination is also possible.
Incidentally, as a result of combination of the first and second aspects of the present invention, in the N-channel MOS field-effect transistor formed on the SOI substrate having the 1.5-xcexcm thick silicon layer and the 3.0-xcexcm thick buried oxide film, the breakdown voltage of 340 V was obtained. This voltage value is obtained as the result of the computer simulation.
Herein, a description was directed to both of the cases where the SOI substrate with the 1.5-xcexcm thick silicon layer has the 0.5-xcexcm thick buried oxide film and the 3.0-xcexcm buried oxide film. In both of the cases, the effect of the improved breakdown voltage was obtained. As a matter of course, the thickness of the silicon layer may be set to any value more or less than 1.5 xcexcm. Similarly, the thickness of the buried oxide film may also be set to any value. The effect of the improved breakdown voltage can be obtained irrespective of the thickness of the silicon layer and the thickness of the buried oxide film.
According to the present invention, an increased breakdown voltage N-channel MOS field-effect transistor, an increased breakdown voltage P-channel MOS field-effect transistor, an increased breakdown voltage NPN transistor, and an increased breakdown voltage PNP transistor can be obtained without increasing the thickness of a silicon layer and the thickness of a buried oxide film.
Other objects, features and advantages of the invention will become apparent-from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.